// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_topic_sche_mem_s_cfg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:26:22 Create file
// ******************************************************************************

#ifndef __STARS_TOPIC_SCHE_MEM_S_CFG_REG_OFFSET_H__
#define __STARS_TOPIC_SCHE_MEM_S_CFG_REG_OFFSET_H__

/* STARS_TOPIC_SCHE_MEM_S_CFG Base address of Module's Register */
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE                       (0x4800000)

/******************************************************************************/
/*                      SOC STARS_TOPIC_SCHE_MEM_S_CFG Registers' Definitions                            */
/******************************************************************************/

#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL_ENABLE_CTRL_S_0_REG  (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20000) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL_ENABLE_CTRL_S_1_REG  (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20004) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL_ENABLE_CTRL_S_2_REG  (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20008) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL_DISABLE_CTRL_S_0_REG (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20040) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL_DISABLE_CTRL_S_1_REG (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20044) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL_DISABLE_CTRL_S_2_REG (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20048) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL0_STATUS_S_REG        (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20080) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL1_STATUS_S_REG        (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20084) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_ACPU_SLOT_POOL2_STATUS_S_REG        (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20088) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL_ENABLE_CTRL_S_0_REG  (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20100) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL_ENABLE_CTRL_S_1_REG  (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20104) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL_ENABLE_CTRL_S_2_REG  (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20108) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL_DISABLE_CTRL_S_0_REG (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20140) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL_DISABLE_CTRL_S_1_REG (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20144) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL_DISABLE_CTRL_S_2_REG (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20148) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL0_STATUS_S_REG        (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20180) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL1_STATUS_S_REG        (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20184) 
#define SOC_STARS_TOPIC_SCHE_MEM_S_CFG_STARS_TOPIC_CCPU_SLOT_POOL2_STATUS_S_REG        (SOC_STARS_TOPIC_SCHE_MEM_S_CFG_BASE + 0x20188) 

#endif // __STARS_TOPIC_SCHE_MEM_S_CFG_REG_OFFSET_H__
